The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Dec. 12, 2014
Applicant:

Via Alliance Semiconductor Co., Ltd., Shanghai, CN;

Inventors:

G. Glenn Henry, Austin, TX (US);

Dinesh K. Jain, Austin, TX (US);

Stephan Gaskins, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/12 (2016.01); G06F 12/08 (2016.01); G06F 1/32 (2006.01); G06F 9/445 (2006.01); G06F 15/177 (2006.01); G11C 7/20 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); G06F 9/44 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0893 (2013.01); G06F 1/3275 (2013.01); G06F 8/66 (2013.01); G06F 12/0811 (2013.01); G06F 12/12 (2013.01); G06F 15/177 (2013.01); G11C 7/20 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); G06F 9/4403 (2013.01); G06F 2212/222 (2013.01); G06F 2212/283 (2013.01); G06F 2212/601 (2013.01); G06F 2212/69 (2013.01); G11C 2029/4402 (2013.01); Y02B 60/183 (2013.01);
Abstract

An apparatus includes a programmer, a stores, and a plurality of cores. The programmer programs a fuse array with compressed configuration data. The stores provides for storage and access of decompressed configuration data sets. Each of a plurality of cores is coupled to the fuse array. One of the cores is accesses the fuse array upon power-up/reset to decompress and store decompressed configuration data sets for one or more cache memories. Each of the cores includes reset logic and sleep logic. The reset logic employs the decompressed configuration data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following the power gating event.


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