The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Mar. 30, 2012
Applicants:

Vjekoslav Svilan, Sunnyvale, CA (US);

Michael Zelikson, Haifa, IL;

Kelvin Kwan, Santa Clara, CA (US);

Naveen Neelakantam, Mountain View, CA (US);

Norbert Unger, Braunschweig, DE;

Inventors:

Vjekoslav Svilan, Sunnyvale, CA (US);

Michael Zelikson, Haifa, IL;

Kelvin Kwan, Santa Clara, CA (US);

Naveen Neelakantam, Mountain View, CA (US);

Norbert Unger, Braunschweig, DE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/3203 (2013.01); G06F 1/3287 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1282 (2013.01);
Abstract

In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.


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