The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2017
Filed:
Mar. 04, 2013
Applicant:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Inventors:
Hirokazu Ishida, Kanagawa, JP;
Kenichiro Toratani, Kanagawa, JP;
Assignee:
KABUSHIKI KAISHA TOSHIBA, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66825 (2013.01); H01L 21/28273 (2013.01); H01L 27/11521 (2013.01); H01L 29/401 (2013.01); H01L 29/42332 (2013.01); H01L 29/788 (2013.01);
Abstract
A semiconductor device fabrication method includes forming a tunnel insulating film on a substrate containing silicon, forming a floating gate on the tunnel insulating film, forming an integral insulating film on the floating gate, and forming a control gate on the integral insulating film. The floating gate is formed on the tunnel insulating film by forming a seed layer containing amorphous silicon on the tunnel insulating film, forming an impurity later containing adsorbed boron or germanium on the seed layer, and forming a cap layer containing silicon on the impurity layer.