The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Apr. 27, 2015
Applicant:

Etron Technology, Inc., Hsinchu, TW;

Inventors:

Bor-Doou Rong, Hsinchu County, TW;

Chun Shiah, Hsinchu City, TW;

Assignee:

Etron Technology, Inc., Hsinchu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/538 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 23/544 (2006.01); H01L 21/66 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 21/768 (2013.01); H01L 21/78 (2013.01); H01L 23/5381 (2013.01); H01L 23/544 (2013.01); H01L 24/03 (2013.01); H01L 22/32 (2013.01); H01L 27/10897 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.


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