The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Sep. 25, 2014
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Margaret A. Szymanowski, Chandler, AZ (US);

Kimberly J. Foxx, Phoenix, AZ (US);

Robert A. Pryor, Mesa, AZ (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/332 (2006.01); H01L 23/00 (2006.01); H01L 23/66 (2006.01); H03F 1/02 (2006.01); H03F 1/56 (2006.01); H03F 3/193 (2006.01);
U.S. Cl.
CPC ...
H01L 24/85 (2013.01); H01L 23/66 (2013.01); H03F 1/0288 (2013.01); H03F 1/565 (2013.01); H03F 3/193 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/181 (2013.01); H03F 2200/36 (2013.01); H03F 2200/451 (2013.01);
Abstract

An embodiment of a packaged RF amplifier device includes a device substrate, a transistor die coupled to the device substrate, and an isolation structure coupled to the transistor die. The transistor die has a top die surface, a bottom die surface, a semiconductor substrate, first and second transistors formed in the semiconductor substrate, a conductive structure at the top die surface and positioned between the first and second transistors, and a low resistance path that extends vertically through the semiconductor substrate between the conductive structure and the bottom die surface. The isolation structure is coupled to the conductive structure and extends into an area above the top die surface between the first and second transistors. The isolation structure may be a wirebond fence, a conductive wall, conductive pillars or vias, or a plated trench that extends vertically upward from the conductive structure. The device may be encapsulated with molding compound.


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