The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Sep. 29, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventor:

Walter Parmon, Chandler, AZ (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01P 5/02 (2006.01); H01L 23/552 (2006.01); H01L 23/498 (2006.01); H01L 23/66 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/66 (2013.01); H01L 2223/6683 (2013.01);
Abstract

A method and apparatus are provided for manufacturing a packaged electronic device () which includes a carrier substrate () in which conductive interconnect paths () extend between first and second opposed surfaces, an integrated circuit die () affixed to the first surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, and an array of conductors (), such as BGA, LGA, PGA, C4 bump or flip chip conductors, affixed to the second surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, where the array comprising a signal feed ball () and an array of shielding ground balls () surrounding the signal feed ball.


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