The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

May. 31, 2016
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Thomas Evan Wilson, Laurel, MD (US);

Eric Harris Naviasky, Ellicott City, MD (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/409 (2006.01); H03K 19/003 (2006.01); H03K 17/14 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G11C 11/409 (2013.01); G11C 11/4076 (2013.01); H03K 19/00315 (2013.01); H03K 17/145 (2013.01);
Abstract

Embodiments relate to systems, methods and computer readable media to enable design and creation of memory driver circuitry using a voltage translation capacitor. One embodiment is high speed level translation memory driver apparatus comprising a plurality of field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) logic gates to drive the FETs, and a voltage translation capacitor with a first terminal of the voltage translation capacitor connected to an output of a second CMOS logic gate and a second terminal of the voltage translation capacitor connected to a gate terminal of a first P-type FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.


Find Patent Forward Citations

Loading…