The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2017
Filed:
Nov. 18, 2014
Applicant:
Mediatek Inc., Hsin-Chu, TW;
Inventors:
Assignee:
MEDIATEK INC., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); G06F 17/5081 (2013.01); G06F 2217/40 (2013.01); G06F 2217/78 (2013.01); H01L 24/06 (2013.01); H01L 24/14 (2013.01); H01L 2224/0612 (2013.01); H01L 2224/1412 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06517 (2013.01); H01L 2924/15311 (2013.01);
Abstract
A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed to obtain a total number of micro bumps of the flip-chip according to the information, and obtain a minimum conductance of each of the power pins of the flip-chip according to a bump placement of the micro bumps of the flip-chip. A chip-interposer routing procedure is performed to obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the minimum conductance of the power pins of the flip-chip.