The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2017
Filed:
Mar. 23, 2015
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/763 (2006.01); H01L 21/8238 (2006.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 29/94 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/04 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/02513 (2013.01); H01L 21/02532 (2013.01); H01L 21/28035 (2013.01); H01L 28/60 (2013.01); H01L 29/16 (2013.01); H01L 29/945 (2013.01); H01L 21/763 (2013.01); H01L 21/823828 (2013.01); H01L 29/51 (2013.01); H01L 29/7833 (2013.01);
Abstract
In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.