The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2017
Filed:
Oct. 23, 2013
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Yu-Hao Hu, Kaohsiung, TW;
Yi-Tzu Chen, Hsinchu, TW;
Hao-I Yang, Hsinchu, TW;
Cheng-Jen Chang, Taoyuan, TW;
Geng-Cing Lin, Taipei, TW;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/105 (2006.01); G11C 7/18 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01); G11C 5/14 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1052 (2013.01); G11C 7/18 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01); G11C 5/145 (2013.01); G11C 5/147 (2013.01); G11C 11/4074 (2013.01);
Abstract
A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory column having the second bit line, a second word line and a third bit line. The first memory column and the second memory column are configured to share the second bit line. The sharing of the second bit line facilitates sharing one or more memory array components between the first memory column and the second memory column.