The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Dec. 23, 2011
Applicants:

Elmoustapha Ould-ahmed-vall, Chandler, AZ (US);

Mostafa Hagog, Kaukab, IL;

Robert Valentine, Kiryat Tivon, IL;

Amit Gradstein, Binyamina, IL;

Simon Rubanovich, Haifa, IL;

Zeev Sperber, Zichron Yackov, IL;

Inventors:

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Mostafa Hagog, Kaukab, IL;

Robert Valentine, Kiryat Tivon, IL;

Amit Gradstein, Binyamina, IL;

Simon Rubanovich, Haifa, IL;

Zeev Sperber, Zichron Yackov, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); G06F 9/302 (2006.01); G06F 15/78 (2006.01); G06F 9/30 (2006.01); G06F 7/544 (2006.01); G06F 9/38 (2006.01); G06F 7/50 (2006.01);
U.S. Cl.
CPC ...
G06F 15/78 (2013.01); G06F 7/544 (2013.01); G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 7/50 (2013.01); G06F 9/3836 (2013.01); G06F 9/3877 (2013.01); G06F 2207/5442 (2013.01);
Abstract

Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.


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