The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Dec. 12, 2014
Applicant:

Via Alliance Semiconductor Co., Ltd., Shanghai, CN;

Inventors:

G. Glenn Henry, Austin, TX (US);

Dinesh K. Jain, Austin, TX (US);

Stephan Gaskins, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 1/32 (2006.01); G06F 12/12 (2016.01); G06F 9/44 (2006.01); G06F 9/445 (2006.01); G06F 15/177 (2006.01); G11C 7/20 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0893 (2013.01); G06F 1/3275 (2013.01); G06F 8/66 (2013.01); G06F 9/4403 (2013.01); G06F 12/0811 (2013.01); G06F 12/12 (2013.01); G06F 15/177 (2013.01); G11C 7/20 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); G06F 2212/222 (2013.01); G06F 2212/283 (2013.01); G06F 2212/601 (2013.01); G06F 2212/69 (2013.01); G11C 2029/4402 (2013.01); Y02B 60/183 (2013.01);
Abstract

An apparatus including a device programmer, a stores, and a plurality of cores. The device programmer programs a semiconductor fuse array with compressed configuration data for a plurality of cores disposed on a die. The stores has a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores is configured to access the semiconductor fuse array upon power-up/reset to read and decompress the configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. The plurality of cores each has sleep logic that is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event.


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