The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Feb. 10, 2014
Applicant:

Virident Systems, Llc, San Jose, CA (US);

Inventors:

Ashwin Narasimha, Sunnyvale, CA (US);

Vibhor Patel, Bangalore, IN;

Sandeep Sharma, Jammu, IN;

Ajith Kumar, Bangalore, IN;

Assignee:

Virident Systems, LLC, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 12/02 (2006.01); G11C 16/26 (2006.01); G06F 13/16 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 13/1657 (2013.01); G06F 13/1694 (2013.01); G11C 16/26 (2013.01); G06F 11/076 (2013.01); G06F 2212/7201 (2013.01); Y02B 60/1225 (2013.01); Y02B 60/1228 (2013.01);
Abstract

A memory apparatus and methods are provided for preventing read errors on weak pages in a non-volatile memory system. In one example, a method includes identifying a weak page in a non-volatile memory device along a word line, wherein the weak page is partially written with at least some data; buffering data associated with the weak page to a weak page buffer that is coupled in communication with the non-volatile memory device; determining that an amount of data in the weak page buffer has reached a predetermined data level; and writing the data from the weak page buffer into the weak page along the word line in the non-volatile memory device.


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