The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Mar. 31, 2015
Applicant:

Cavium, Inc., San Jose, CA (US);

Inventors:

Ajeer Salil Pudiyapura, Sunnyvale, CA (US);

Kishore Badari Atreya, San Jose, CA (US);

Ravindran Suresh, San Jose, CA (US);

Assignee:

Cavium, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2006.01); G06F 9/45 (2006.01); G06F 15/76 (2006.01); G06F 9/30 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 8/33 (2013.01); G06F 8/314 (2013.01); G06F 8/41 (2013.01); G06F 8/427 (2013.01); G06F 8/443 (2013.01); G06F 8/445 (2013.01); G06F 8/447 (2013.01); G06F 8/4434 (2013.01); G06F 8/451 (2013.01); G06F 8/70 (2013.01); G06F 9/30145 (2013.01); G06F 15/7825 (2013.01); G06F 15/76 (2013.01);
Abstract

A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.


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