The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Dec. 21, 2015
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Masashi Kijima, Aichi, JP;

Satoru Mizuta, Aichi, JP;

Tsutomu Tanii, Aichi, JP;

Hiroyuki Matsunami, Kasugai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/38 (2006.01); H03M 1/00 (2006.01); H03M 1/46 (2006.01);
U.S. Cl.
CPC ...
H03M 1/002 (2013.01); H03M 1/38 (2013.01); H03M 1/462 (2013.01); H03M 1/466 (2013.01);
Abstract

In an example embodiment, an analog-digital converter includes digital-analog converter, a comparator, and a register. The digital-analog converter is configured to output a differential voltage between a reference voltage and a voltage of an analog signal. The comparator is configured to output a comparison signal corresponding to the differential voltage output by the digital-analog converter. The register is configured to cause the digital-analog converter to generate N pairs of differential voltages (N≧1), to cause the digital-analog converter to generate an (N+1)pair of differential voltages by causing one of a positive side and a negative side of the digital-analog converter to output an (N+1)differential voltage and causing the other of the positive side and the negative side to output a differential voltage equal to the Ndifferential voltage as an (N+1)differential voltage, and to output a digital signal corresponding to a comparison signal having a smallest voltage among (N+1) comparison signals.


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