The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2017
Filed:
Sep. 24, 2015
Qualcomm Incorporated, San Diego, CA (US);
Satyanarayana Sahu, San Diego, CA (US);
Xiangdong Chen, San Diego, CA (US);
Venugopal Boynapalli, San Marcos, CA (US);
Hyeokjin Bruce Lim, San Diego, CA (US);
Mukul Gupta, San Diego, CA (US);
Hananel Kang, San Diego, CA (US);
Chih-lung Kao, San Diego, CA (US);
Radhika Guttal, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating.