The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Mar. 01, 2012
Applicants:

Nicholas P. Cowley, Wroughton, GB;

Andrew D. Talbot, Chieveley, GB;

Mark Mudd, Wiltshire, GB;

Stephen J. Spinks, Swindon, GB;

Keith Pinson, Swindon, GB;

Colin L. Perry, Swindon, GB;

Alan J. Martin, Plymouth, GB;

Chi Man Kan, Swindon, GB;

Matthew T. Aitken, Swindon, GB;

William L. Barber, Bampton, GB;

Isaac Ali, Berkshire, GB;

Inventors:

Nicholas P. Cowley, Wroughton, GB;

Andrew D. Talbot, Chieveley, GB;

Mark Mudd, Wiltshire, GB;

Stephen J. Spinks, Swindon, GB;

Keith Pinson, Swindon, GB;

Colin L. Perry, Swindon, GB;

Alan J. Martin, Plymouth, GB;

Chi Man Kan, Swindon, GB;

Matthew T. Aitken, Swindon, GB;

William L. Barber, Bampton, GB;

Isaac Ali, Berkshire, GB;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H02M 3/156 (2006.01); H02M 3/157 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 3/158 (2013.01); H02M 2001/0032 (2013.01); H02M 2001/0045 (2013.01); Y02B 70/16 (2013.01);
Abstract

A dual mode voltage regulator according to one embodiment includes a passive regulator circuit, a switching regulator circuit, and a controller circuit configured to determine parameters of an external select input. The controller is configured to selectively couple, on a cold boot up, either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load based on the determination of parameters.


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