The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Jun. 22, 2016
Applicant:

Socionext Inc., Yokohama-shi, Kanagawa, JP;

Inventors:

Yosuke Shimamune, Kawasaki, JP;

Akira Katakami, Kawasaki, JP;

Akiyoshi Hatada, Kawasaki, JP;

Masashi Shima, Kawasaki, JP;

Naoyoshi Tamura, Kawasaki, JP;

Assignee:

SOCIONEXT INC., Yokohama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0328 (2006.01); H01L 31/0336 (2006.01); H01L 31/072 (2012.01); H01L 31/109 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/665 (2013.01); H01L 29/66636 (2013.01);
Abstract

A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.


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