The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Mar. 27, 2014
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, JP;

Inventors:

Shiro Hino, Tokyo, JP;

Naruhisa Miura, Tokyo, JP;

Masayuki Imaizumi, Tokyo, JP;

Kohei Ebihara, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/47 (2006.01); H01L 29/872 (2006.01); H01L 29/12 (2006.01); H01L 29/36 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7806 (2013.01); H01L 29/0619 (2013.01); H01L 29/0696 (2013.01); H01L 29/0865 (2013.01); H01L 29/1095 (2013.01); H01L 29/12 (2013.01); H01L 29/1608 (2013.01); H01L 29/36 (2013.01); H01L 29/47 (2013.01); H01L 29/78 (2013.01); H01L 29/872 (2013.01);
Abstract

A device that increases a value of current flowing through a whole chip until a p-n diode in a unit cell close to a termination operates and reduces a size of the chip and a cost of the chip resulting from the reduced size. The device includes a second well region located to sandwich the entirety of a plurality of first well regions therein in plan view, a third separation region located to penetrate the second well region from a surface layer of the second well region in a depth direction, and a second Schottky electrode provided on the third separation region.


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