The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2017
Filed:
Oct. 22, 2013
Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;
Abstract
A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (); b. forming a fin () on the substrate; c. forming an shallow trench isolation structure () on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer () on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region () under the sacrificial gate vacancy; i. etching the shallow trench isolation structure () under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure () levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy. Some advantages of the current invention may be, harmful effects produced in the source/drain regions by the triangle fin structure are eliminated, the device performance is improved, and the complexity of the process is reduce.