The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Dec. 11, 2014
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Romain Esteve, Treffen am Ossiacher, AT;

Dethard Peters, Hoechstadt, DE;

Wolfgang Bergner, Klagenfurt, AT;

Ralf Siemieniec, Villach, AT;

Thomas Aichinger, Villach, AT;

Daniel Kueck, Villach, AT;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/324 (2006.01); H01L 21/04 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66734 (2013.01); H01L 21/02236 (2013.01); H01L 21/045 (2013.01); H01L 21/049 (2013.01); H01L 21/0465 (2013.01); H01L 21/0475 (2013.01); H01L 21/31111 (2013.01); H01L 21/324 (2013.01); H01L 21/3247 (2013.01); H01L 29/4236 (2013.01); H01L 29/66068 (2013.01); H01L 29/1608 (2013.01);
Abstract

A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.


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