The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Jan. 06, 2016
Applicant:

Inotera Memories, Inc., Taoyuan, TW;

Inventor:

Yi-Jen Lo, New Taipei, TW;

Assignee:

INOTERA MEMORIES, INC., Taoyuan, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01); H01L 23/485 (2006.01); H01L 23/00 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H01L 23/481 (2013.01); H01L 23/485 (2013.01); H01L 24/08 (2013.01); H01L 24/14 (2013.01); H01L 28/75 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05147 (2013.01);
Abstract

A fan-out wafer-level-package (FOWLP) is provided. The FOWLP includes a redistribution layer (RDL) comprising a dielectric layer and a first metal layer; a passive device in the first metal layer; a first passivation layer covering a top surface of the RDL; a second passivation layer covering a bottom surface of the RDL; a chip mounted on the first passivation layer; a molding compound around the chip and on the first passivation layer; a via opening penetrating through the second passivation layer, the dielectric layer, and the second passivation layer, thereby exposing a terminal of the chip; a contact opening in the second passivation layer; and a second metal layer in the via opening and the contact opening to electrically connect one electrode of the passive device with the terminal of the chip.


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