The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Nov. 18, 2013
Applicant:

Amkor Technology, Inc., Chandler, AZ (US);

Inventors:

Ronald Patrick Huemoeller, Gilbert, AZ (US);

Curtis Zwenger, Chandler, AZ (US);

David Jon Hiner, Chandler, AZ (US);

Corey Reichman, Mesa, AZ (US);

Assignee:

Amkor Technology, Inc., Tempe, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/762 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 24/03 (2013.01); H01L 21/48 (2013.01); H01L 21/76251 (2013.01); H01L 23/49816 (2013.01); H01L 23/5383 (2013.01); H01L 24/80 (2013.01);
Abstract

Methods for an embedded die panel are disclosed and may include fabricating a first layered structure by: forming first redistribution layers on a first carrier, forming a first dielectric layer on the first redistribution layers and carrier, forming a mask pattern on the first dielectric layer exposing a portion of the first dielectric layer, forming a second dielectric layer on the exposed portion of the first dielectric layer, forming vias in the first and second dielectric layers, and forming second redistribution layers on the second dielectric layer. The mask pattern may be removed forming a die cavity defined by the second dielectric layer. A second layered structure coupled to the first layered structure may be formed comprising a second carrier, a third dielectric layer, third and fourth redistribution layers on opposite surfaces of the third dielectric layer, and a semiconductor die.


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