The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2017
Filed:
Jun. 26, 2015
Globalfoundries, Inc., Grand Cayman, KY;
Stmicroelectronics, Inc., Coppell, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Ming He, Menands, NY (US);
Seowoo Nam, Delmar, NY (US);
Yann Mignot, Slingerlands, NY (US);
Jim Kelly, Schenectady, NY (US);
Raghuveer Patlotta, Guilderland, NY (US);
Theodorus Standaert, Clifton Park, NY (US);
GLOBALFOUNDRIES, INC., Grand Cayman, KY;
STMICROELECTRONICS, INC., Coppell, TX (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect in a first interlayer dielectric. A first cap is formed overlying the first interlayer dielectric adjacent to the interconnect, and a second interlayer dielectric is formed overlying the first interlayer dielectric, the interconnect, and the cap. A contact is formed through the second interlayer dielectric, where the contact includes an overlap region and a connection region. The overlap region directly overlies the first interlayer dielectric adjacent to the interconnect, and the connection region directly contacts the interconnect. The first cap is positioned between the overlap region and the first interlayer dielectric.