The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Dec. 23, 2010
Applicants:

Ki-hun Jeong, Cheonan-si, KR;

Do-hyun Kim, Seongnam-si, KR;

Dong-hoon Lee, Seoul, KR;

Kap-soo Yoon, Seoul, KR;

Jae-ho Choi, Seoul, KR;

Sung-hoon Yang, Seoul, KR;

Pil-sang Yun, Seoul, KR;

Seung-mi Seo, Seoul, KR;

Inventors:

Ki-Hun Jeong, Cheonan-si, KR;

Do-Hyun Kim, Seongnam-si, KR;

Dong-Hoon Lee, Seoul, KR;

Kap-Soo Yoon, Seoul, KR;

Jae-Ho Choi, Seoul, KR;

Sung-Hoon Yang, Seoul, KR;

Pil-Sang Yun, Seoul, KR;

Seung-Mi Seo, Seoul, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/12 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 29/78606 (2013.01); H01L 29/78633 (2013.01);
Abstract

The present invention discloses a thin film transistor (TFT), a method for manufacturing the TFT, and a display substrate using the TFT that may prevent degradation of the characteristics of an oxide semiconductor contained in the TFT by blocking external light from entering a channel region of the oxide semiconductor. The TFT includes an oxide semiconductor layer; a protective layer overlapping a channel region of the oxide semiconductor layer; an opaque layer disposed between the oxide semiconductor layer and the protective layer; a source electrode contacting a first side of the oxide semiconductor layer; a drain electrode contacting a second side of the oxide semiconductor layer and facing the source electrode across the channel region; a gate electrode to apply an electric field to the oxide semiconductor layer; and a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer.


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