The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9570612 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 14, 2017

Filed:

Jun. 27, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Tetsu Ohtou, Hsinchu, TW;

Jiun-Peng Wu, Hsinchu, TW;

Ching-Wei Tsai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 29/40 (2006.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/41 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7849 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 29/0676 (2013.01); H01L 29/1054 (2013.01); H01L 29/401 (2013.01); H01L 29/413 (2013.01); H01L 29/42376 (2013.01); H01L 29/66439 (2013.01); H01L 29/66666 (2013.01); H01L 29/775 (2013.01); H01L 29/7827 (2013.01); H01L 29/42392 (2013.01);
Abstract

Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region (); a drain region () aligned substantially vertically to the source region; a channel structure () bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure () arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels () extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor () interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.


Find Patent Forward Citations

Ohtou, Tetsu. (2017). Method and structure for straining carrier channel in vertical gate all-around device (U.S. Patent No. 9570612). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9570612

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