The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2017
Filed:
Jun. 03, 2015
Applicants:
Borna J. Obradovic, Leander, TX (US);
Robert C. Bowen, Austin, TX (US);
Mark S. Rodder, Dallas, TX (US);
Inventors:
Borna J. Obradovic, Leander, TX (US);
Robert C. Bowen, Austin, TX (US);
Mark S. Rodder, Dallas, TX (US);
Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/786 (2006.01); H01L 29/20 (2006.01); B82Y 40/00 (2011.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7845 (2013.01); B82Y 40/00 (2013.01); H01L 29/0673 (2013.01); H01L 29/20 (2013.01); H01L 29/42392 (2013.01); H01L 29/517 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01); H01L 29/78681 (2013.01); H01L 29/78696 (2013.01);
Abstract
A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.