The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Jul. 16, 2013
Applicant:

Hitachi, Ltd., Chiyoda-ku, Tokyo, JP;

Inventors:

Yuki Mori, Tokyo, JP;

Toshiyuki Mine, Tokyo, JP;

Hiroshi Miki, Tokyo, JP;

Mieko Matsumura, Tokyo, JP;

Hirotaka Hamamura, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 31/0312 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/16 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7802 (2013.01); H01L 29/1608 (2013.01); H01L 29/45 (2013.01); H01L 29/4925 (2013.01); H01L 29/4933 (2013.01); H01L 29/66068 (2013.01);
Abstract

Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PFhaving the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PFformed in contact with the polycrystalline silicon film PFand having any thickness.


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