The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Sep. 11, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Harry-Hak-Lay Chuang, Zhubei, TW;

Yu-Hsiung Wang, Zhubei, TW;

Chen-Chin Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 49/02 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 28/90 (2013.01); H01L 27/10805 (2013.01); H01L 27/1157 (2013.01);
Abstract

Some embodiments of the present disclosure relate to an integrated circuit (IC) arranged on a semiconductor substrate, which includes a flash region, a capacitor region, and a logic region. An upper substrate surface of the capacitor region is recessed relative to respective upper substrate surfaces of the flash and logic regions, respectively. A capacitor, which includes a polysilicon bottom electrode, a conductive top electrode arranged over the polysilicon bottom electrode, and a capacitor dielectric separating the bottom and top electrodes; is disposed over the recessed upper substrate surface of the capacitor region. A flash memory cell is disposed over the upper substrate surface of the flash region. The flash memory cell includes a select gate having a planarized upper surface that is co-planar with a planarized upper surface of the top electrode of the capacitor.


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