The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Jun. 18, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Hyo-Jin Kwon, Seoul, KR;

Dae-Seok Byeon, Seongnam-si, KR;

Yeong-Taek Lee, Seoul, KR;

Chi-Weon Yoon, Seoul, KR;

Yong-Kyu Lee, Hwaseong-si, KR;

Hyun-Kook Park, Anyang-si, KP;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/00 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/76 (2013.01); G11C 11/16 (2013.01); G11C 11/1653 (2013.01); G11C 11/1675 (2013.01); G11C 11/1677 (2013.01); G11C 11/1695 (2013.01); G11C 13/0002 (2013.01); G11C 13/0023 (2013.01); G11C 13/0059 (2013.01); G11C 13/0064 (2013.01); G11C 13/0069 (2013.01); G11C 29/808 (2013.01); G11C 2029/4402 (2013.01); G11C 2213/71 (2013.01);
Abstract

A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.


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