The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Aug. 21, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Jae-Yun Lee, Anyang-si, KR;

Woo-Jung Sun, Seoul, KR;

Kwang-Jin Lee, Hwaseong-si, KR;

Dong-Hoon Jeong, Changwon-si, KR;

Beak-Hyung Cho, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 13/00 (2006.01); G11C 11/418 (2006.01); G11C 11/417 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 7/1075 (2013.01); G11C 11/417 (2013.01); G11C 11/418 (2013.01); G11C 13/0026 (2013.01); G11C 13/0038 (2013.01); G11C 13/0069 (2013.01); G11C 2207/2209 (2013.01); G11C 2207/229 (2013.01); G11C 2207/2281 (2013.01); G11C 2213/71 (2013.01); G11C 2213/72 (2013.01);
Abstract

Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.


Find Patent Forward Citations

Loading…