The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9569882 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 14, 2017

Filed:

Dec. 20, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert L. Farrell, Granite Bay, CA (US);

Vasanth Ranganathan, Tigard, OR (US);

Karol A. Szerszen, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06T 15/40 (2011.01);
U.S. Cl.
CPC ...
G06T 15/405 (2013.01); G06T 2210/12 (2013.01);
Abstract

One or more apparatus and method for multi-pixel/sample level depth testing in a graphics processor is described. In embodiments, a bounding-box of variable size over which a depth test is to be performed is determined based on the pattern of lit pixels or samples within rasterizer tile. A multi-corner depth test may be performed between a source depth data plane and a destination depth plane within a source depth data bound where destination depth data is continuous within the source data bound. A range-based depth test may be performed in response to the destination data being discontinuous. Source depth data prevailing in the depth test may be stored in a compressed plane equation format in response to the source data being continuous within the source data bound, and may be stored as min/max depth data if discontinuous.


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