The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Mar. 27, 2013
Applicant:

Hitachi, Ltd., Chiyoda-ku, Tokyo, JP;

Inventors:

Yutaka Uematsu, Tokyo, JP;

Satoshi Muraoka, Tokyo, JP;

Hideki Osaka, Tokyo, JP;

Masabumi Shibata, Tokyo, JP;

Yuusuke Fukumura, Tokyo, JP;

Satoru Watanabe, Tokyo, JP;

Hiroshi Kakita, Tokyo, JP;

Akio Idei, Tokyo, JP;

Hitoshi Ueno, Tokyo, JP;

Takayuki Ono, Tokyo, JP;

Takashi Miyagawa, Tokyo, JP;

Michinori Naito, Tokyo, JP;

Taishi Sumikura, Tokyo, JP;

Yuichi Fukuda, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 14/00 (2006.01); G06F 3/06 (2006.01); G11C 5/04 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/068 (2013.01); G06F 3/0611 (2013.01); G06F 3/0629 (2013.01); G06F 13/1694 (2013.01); G11C 5/04 (2013.01); G11C 7/10 (2013.01);
Abstract

When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.


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