The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2017
Filed:
Dec. 04, 2014
Marvell Israel (M.i.s.l) Ltd., Yokneam, IL;
Dan Azeroual, Kiriat Ata, IL;
Eldad Bar-Lev, Kiryat Tivon, IL;
Marvell Israel (M.I.S.L) Ltd., Yokneam, IL;
Abstract
Aspects of the disclosure provide a printed circuit board (PCB) structure. The PCB structure includes a plurality of dielectric layers including an outer layer, a second layer disposed immediately below the outer layer, at least one first power plane disposed on at least one first internal layer of the PCB structure, and at least one first ground plane disposed on at least one second internal layer of the PCB structure. The PCB structure further includes an array of buried vias passing through at least the second layer configured to respectively connect power pads disposed on the second layer to the at least one first power plane and to connect ground pads disposed on the second layer to the at least one first ground plane. The array of buried vias is defined by columns of pads in which a respective column includes either power pads or ground pads, columns of power pads alternate with columns of ground pads, and pads of at least one of a column of power pads and a column of ground pads are staggered with respect to other pads of the at least one of the column of power pads and the column of ground pads. The PCB structure further includes an array of outer layer vias passing through the outer layer and configured to provide an electrical connection between one or more circuit components disposed on the outer layer and the second layer.