The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2017
Filed:
Jul. 02, 2012
Shenqing Fang, Fremont, CA (US);
Tung-sheng Chen, Cupertino, CA (US);
Tim Thurgate, Sunnyvale, CA (US);
Di LI, Highland, CA (US);
Shenqing Fang, Fremont, CA (US);
Tung-Sheng Chen, Cupertino, CA (US);
Tim Thurgate, Sunnyvale, CA (US);
Di Li, Highland, CA (US);
CYPRESS SEMICONDUCTOR CORPORATION, San Jose, CA (US);
Abstract
A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.