The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2017

Filed:

Dec. 26, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bruce Querbach, Hillsboro, OR (US);

Theodore Z. Schoenborn, Portland, OR (US);

David J. Zimmerman, El Dorado Hills, CA (US);

David G. Ellis, Tualatin, OR (US);

Christopher W. Hampson, Hillsboro, OR (US);

Ifar Wan, Hillsboro, OR (US);

Yulan Zhang, Hillsboro, OR (US);

Ramakrishna Mallela, Hillsboro, OR (US);

William K. Lui, Portland, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/263 (2006.01); G06F 11/27 (2006.01); G11C 11/406 (2006.01); G11C 29/00 (2006.01); G11C 29/36 (2006.01); G11C 29/44 (2006.01); G11C 29/10 (2006.01);
U.S. Cl.
CPC ...
G11C 29/36 (2013.01); G06F 11/263 (2013.01); G11C 29/10 (2013.01); G11C 29/4401 (2013.01); G06F 11/27 (2013.01); G11C 11/406 (2013.01); G11C 29/72 (2013.01); G11C 29/78 (2013.01); G11C 2029/4402 (2013.01);
Abstract

In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.


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