The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2017

Filed:

Oct. 19, 2015
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Zhibiao Zhou, Singapore, SG;

Chen-Bin Lin, Taipei, TW;

Chi-Fa Ku, Kaohsiung, TW;

Shao-Hui Wu, Singapore, SG;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 29/04 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); G11C 14/00 (2006.01); H01L 29/786 (2006.01); H01L 27/108 (2006.01); H01L 27/105 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0009 (2013.01); H01L 27/1052 (2013.01); H01L 27/10808 (2013.01); H01L 27/10855 (2013.01); H01L 27/10873 (2013.01); H01L 27/10897 (2013.01); H01L 29/045 (2013.01); H01L 29/24 (2013.01); H01L 29/66477 (2013.01); H01L 29/66969 (2013.01); H01L 29/78 (2013.01); H01L 29/7869 (2013.01);
Abstract

A semiconductor memory device includes a semiconductor substrate having a main surface, at least a first dielectric layer on the main surface of the semiconductor substrate, a first OS FET device and a second OS FET device disposed on the first dielectric layer, at least a second dielectric layer covering the first dielectric layer, the first OS FET device, and the second OS FET device, a first MIM capacitor on the second dielectric layer and electrically coupled to the first OS FET device, and a second MIM capacitor on the second dielectric layer and electrically coupled to the second OS FET device.


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