The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2017

Filed:

Dec. 20, 2012
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Frederick A. Ware, Los Altos Hills, CA (US);

Ely K. Tsern, Los Altos, CA (US);

Brian S. Leibowitz, San Francisco, CA (US);

Wayne Frederick Ellis, Campbell, CA (US);

Akash Bansal, Santa Clara, CA (US);

John Welsford Brooks, San Jose, CA (US);

Kishore Ven Kasamsetty, Cupertino, CA (US);

Assignee:

Rambus Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/42 (2006.01); G11C 7/10 (2006.01); G11C 5/02 (2006.01); G11C 29/02 (2006.01); G06F 13/16 (2006.01); G11C 5/04 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4234 (2013.01); G06F 13/1647 (2013.01); G06F 13/1657 (2013.01); G11C 5/02 (2013.01); G11C 7/10 (2013.01); G11C 7/1072 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 5/04 (2013.01); G11C 2207/2254 (2013.01);
Abstract

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such 'microthreading' provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.


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