The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Dec. 30, 2011
Applicants:

Mark S. Hefty, Aloha, OR (US);

Arlin Davis, Yamhill, OR (US);

Robert Woodruff, Banks, OR (US);

Sayantan Sur, Portland, OR (US);

Shiow-wen Cheng, Portland, OR (US);

Inventors:

Mark S. Hefty, Aloha, OR (US);

Arlin Davis, Yamhill, OR (US);

Robert Woodruff, Banks, OR (US);

Sayantan Sur, Portland, OR (US);

Shiow-wen Cheng, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); H04L 29/08 (2006.01); G06F 13/14 (2006.01); G06F 9/06 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
H04L 67/10 (2013.01); G06F 9/06 (2013.01); G06F 11/1407 (2013.01); G06F 11/1438 (2013.01); G06F 11/1464 (2013.01); G06F 11/1466 (2013.01); G06F 11/1471 (2013.01); G06F 13/14 (2013.01);
Abstract

An embodiment includes a low-latency mechanism for performing a checkpoint on a distributed application. More specifically, an embodiment of the invention includes processing a first application on a compute node, which is included in a cluster, to produce first computed data and then storing the first computed data in volatile memory included locally in the compute node; halting the processing of the first application, based on an initiated checkpoint, and storing first state data corresponding to the halted first application in the volatile memory; storing the first state information and the first computed data in non-volatile memory included locally in the compute node; and resuming processing of the halted first application and then continuing the processing the first application to produce second computed data while simultaneously pulling the first state information and the first computed data from the non-volatile memory to an input/output (IO) node.


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