The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Feb. 09, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Stefano Giaconi, Phoenix, AZ (US);

Mingming Xu, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/03 (2006.01); H04L 7/00 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03057 (2013.01); H04L 7/0041 (2013.01); H04L 7/0058 (2013.01); H04L 7/033 (2013.01); H04L 7/0331 (2013.01); H04L 7/0332 (2013.01); H04L 7/0334 (2013.01); H04L 25/03025 (2013.01); H04L 2025/03598 (2013.01);
Abstract

Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data.


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