The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Nov. 17, 2014
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

National Taiwan University, Taipei, TW;

Inventors:

Der-Chuan Lai, Taipei, TW;

Pin-Shiang Chen, Taipei, TW;

Hung-Chih Chang, Taichung, TW;

Chee-Wee Liu, Taipei, TW;

Samuel C. Pan, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1033 (2013.01); H01L 29/0847 (2013.01); H01L 29/66484 (2013.01); H01L 29/66742 (2013.01); H01L 29/78391 (2014.09); H01L 29/78645 (2013.01);
Abstract

Semiconductor devices and methods of forming the same are provided. A first gate stack is formed over a substrate, wherein the first gate stack comprises a first ferroelectric layer. A source/channel/drain stack is formed over the first gate stack, wherein the source/channel/drain stack comprises one or more 2D material layers. A second gate stack is formed over the source/channel/drain stack, wherein the second gate stack comprises a second ferroelectric layer.


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