The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

May. 29, 2015
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Shizhong Mei, Boise, ID (US);

Victor Wong, Boise, ID (US);

Jeffrey P. Wright, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/481 (2013.01); H01L 24/18 (2013.01); H01L 25/50 (2013.01); H01L 23/5384 (2013.01);
Abstract

Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a logic die can be configured to draw a sum amount of current from a current source. The memory die can include a plurality of through-substrate vias (TSVs) formed in the memory die and configured to provide the sum amount of current to the memory die from the current source. The memory die can include at least two interconnection contacts associated with a first TSV closer to the current source that are not connected. The memory die can include an electrical connection between at least two interconnection contacts associated with a second TSV that is further in distance from the current source than the first TSV.


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