The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Sep. 09, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Stanislav Shwartsman, Haifa, IL;

Robert S. Chappell, Portland, OR (US);

Ronak Singhal, Portland, OR (US);

Ryan L. Carlson, Hillsboro, OR (US);

Raanan Sade, Kibutz Gvat, IL;

Omar M. Shaikh, Portland, OR (US);

Liron Zur, Haifa, IL;

Yiftach Gilad, Givat Ada, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0897 (2013.01); G06F 12/0862 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/402 (2013.01); G06F 2212/602 (2013.01);
Abstract

A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.


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