The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Sep. 28, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ankush Varma, Hillsboro, OR (US);

Krishnakanth V. Sistla, Beaverton, OR (US);

Cesar A. Quiroz, Santa Clara, CA (US);

Vivek Garg, Folsom, CA (US);

Martin T. Rowland, Beaverton, OR (US);

Inder M. Sodhi, Folsom, CA (US);

James S. Burns, Cupertino, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/26 (2013.01); G06F 1/324 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1285 (2013.01);
Abstract

A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.


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