The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2017
Filed:
Mar. 05, 2015
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/00 (2006.01); H03K 23/00 (2006.01); H03K 25/00 (2006.01); H03K 21/02 (2006.01); H03K 5/13 (2014.01);
U.S. Cl.
CPC ...
H03K 21/02 (2013.01); H03K 5/13 (2013.01);
Abstract
A circuit for generating a divided clock signal with a configurable phase offset comprises a first latch circuit adapted to receive a clock signal to be divided; a second latch coupled to an output of the first latch circuit and generating a divided output clock signal; and an initialization circuit coupled to the first latch circuit and the second latch circuit, the initialization circuit coupled to receive an initialization signal. The initialization signal determines a phase offset between the divided output clock signal and the clock signal to be divided. A method of generating a divided clock signal is also described.