The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2017

Filed:

Sep. 25, 2013
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Andrew E. Horch, Seattle, WA (US);

Troy N. Gilliland, Bellevue, WA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); G11C 16/14 (2006.01); G11C 16/04 (2006.01); H01L 27/115 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7883 (2013.01); G11C 16/0441 (2013.01); G11C 16/14 (2013.01); H01L 27/11558 (2013.01); H01L 27/0207 (2013.01);
Abstract

A nonvolatile memory ('NVM') bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.


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