The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2017
Filed:
Mar. 14, 2016
Wei-hsiung Tseng, Seongnam-si, KR;
Ju-youn Kim, Suwon-si, KR;
Seok-jun Won, Seoul, KR;
Jong-ho Lee, Hwaseong-si, KR;
Hye-lan Lee, Hwaseong-si, KR;
Yong-ho Ha, Hwaseong-si, KR;
Wei-Hsiung Tseng, Seongnam-si, KR;
Ju-Youn Kim, Suwon-si, KR;
Seok-Jun Won, Seoul, KR;
Jong-Ho Lee, Hwaseong-si, KR;
Hye-Lan Lee, Hwaseong-si, KR;
Yong-Ho Ha, Hwaseong-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.