The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2017
Filed:
Apr. 08, 2016
Jeng-jye Shau, Palo Alto, CA (US);
Jeng-Jye Shau, Palo Alto, CA (US);
Other;
Abstract
Hybrid Super Threshold (SupVt) circuits are CMOS circuits that can function in two different operation modes: a normal operation mode and a SupVt power saving mode. At normal operation mode, a hybrid SupVt circuit operates in the same ways as typical CMOS circuits. At SupVt mode, the standby leakage current of the circuit is reduced significantly, while the circuit still can function at high speed. Typically, most parts of a hybrid SupVt circuit stay in power saving mode. A circuit block is switched into normal operation mode when it needs to operate at full speed. The resulting circuits are capable of supporting ultra-low power operations without sacrificing performance.