The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2017

Filed:

Dec. 23, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Keith Hazelet, Chandler, AZ (US);

Ziv Kfir, Yavne, IL;

Christopher Thornburg, Gilbert, AZ (US);

Barak Hermesh, Pardes Hana, IL;

Assignee:

INTEL Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J 3/02 (2006.01); H04L 12/835 (2013.01); H04L 12/801 (2013.01); H04L 12/863 (2013.01);
U.S. Cl.
CPC ...
H04L 47/30 (2013.01); H04L 47/29 (2013.01); H04L 47/621 (2013.01);
Abstract

Techniques are disclosed for controlling data transmission in multi-stream digital systems. The techniques disclosed allow an input stream to a conditional access system to be throttled when a FIFO begins to fill up. Each data stream may have its own FIFO, which sends data to a MUX and exports its status to a backpressure rate control module. Multiple seconds worth of data may be stored in a BPRC buffer ahead of the backpressure rate control module prior to being transmitted to a MUX FIFO buffer. The backpressure rate control module may use the cached data to fill available spaces within a MUX FIFO buffer. The determination to forward a data packet may be based on the individual MUX FIFO buffer levels, the sum of all the MUX FIFO buffer levels, and/or one or more configurable threshold values. In some embodiments, individual thresholds may be assigned to each FIFO buffer.


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