The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2017

Filed:

Aug. 27, 2012
Applicants:

Huaxiang Yin, Beijing, CN;

Changliang Qin, Beijing, CN;

Xiaolong MA, Beijing, CN;

Qiuxia Xu, Beijing, CN;

Dapeng Chen, Beijing, CN;

Inventors:

Huaxiang Yin, Beijing, CN;

Changliang Qin, Beijing, CN;

Xiaolong Ma, Beijing, CN;

Qiuxia Xu, Beijing, CN;

Dapeng Chen, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0886 (2013.01); H01L 29/66818 (2013.01); H01L 29/785 (2013.01); H01L 29/7845 (2013.01);
Abstract

The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.


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